1. Field of the Invention
The present invention relates to an ESD (electrostatic discharge) protection device, and more particularly to a SCR (Silicon Controlled Rectifier) device for on-chip ESD protection in shallow-trench-isolation CMOS process.
2. Description of the Prior Art
SCR (Silicon Controlled Rectifier) has been commonly used for on-chip ESD protection. The important feature of SCR is the holding characteristic thereof. In the holding region, the SCR can sustain much high current and clamp the voltage across itself at a very low voltage level. Therefore, the SCR""s are very useful to bypass high current events such as electrostatic discharge (ESD). However, the shallow trench isolation (STI) region in a 0.18 xcexcm CMOS process often has a depth about 0.4xcx9c0.5 xcexcm from the silicon surface, but the N+ or P+ diffusions often have a junction depth of only 0.15xcx9c0.18 xcexcm. Therefore, the deeper STI region in the SCR device will limit the current flowing path, e.g. make a longer current flowing path, in the device structure, and causes the SCR device to have a longer turn-on time, and become un-efficient for on-chip ESD protection. The human-body-model (HBM) ESD events have a rise time of 5xcx9c10 ns, a slow turn-on SCR can not be turned on in time to bypass the ESD event, before the internal devices which are protected by the SCR device are damaged by ESD.
The SCR devices for ESD protection are developed about ten years. The prior SCR devices for ESD protection are shown in FIG. 1 to FIG. 6 and will be described as follows, wherein the prior SCR devices of FIG. 1 to FIG. 4 and FIG. 6 were developed by Texas Instruments Corporation, and FIG. 5 was developed by Industrial Technology Research Institute (ITRI):
In FIG. 1, the lateral SCR structure was disclosed in a US patent of U.S. Pat. No. 5,012,317. The main SCR path is P+(48), N(46), P(44) and N+(52) which form the PNPN structure. When an ESD event is happened on the pad 12 related to ground, the lateral SCR will be triggered on and into the snapback region. In the snapback region, the SCR will hold the voltage across itself at a low voltage level and sustain a high current. Thus, the ESD current can be discharged effectively through this SCR device.
In FIG. 2, the lateral SCR structure was disclosed in a US patent of U.S. Pat. No. 4,939,616. Comparing with the lateral SCR structure of FIG. 1, there is a highly doped region 42 added into the interface of the N well 32 and P substrate 30, and the structure of FIG. 2 is called modified lateral SCR (MLSCR). The interface breakdown voltage of N+42/P substrate 30 is lower than that of the N well 32/P substrate 30, so that the trigger-on voltage of the MLSCR is lower than that of LSCR of FIG. 1. Therefore, the MLSCR can trigger-on faster in ESD events.
In FIG. 3, the lateral SCR structure was disclosed in a US patent of U.S. Pat. No. 5,465,189. The lateral SCR structure of FIG. 3 differs from the MLSCR of FIG. 2 in adding a polysilicon gate 39 between the highly doped regions N3+ and N2+. The polysilicon gate 39 with highly doped regions N3+ and N2+ form an NMOS device. Thus, the distance between the isolated highly doped regions N3+ and N2+ could be shrunk, and the trigger-on voltage of the SCR structure could further lower down. This structure of FIG. 3 is called low voltage trigger SCR (LVTSCR).
In FIG. 4, the lateral SCR structure was disclosed in a US patent of U.S. Pat. No. 5,225,702. The polysilicon electrode 237 instead of the field oxide is used to define the distance between the N+ region 226 and N well 236. Changing this distance could modulate the holding voltage of the SCR. Because the polysilicon electrode could be defined in a smallest area in any generation CMOS process, this SCR has higher design flexibility.
In FIG. 5, the lateral SCR structure was disclosed in a US patent of U.S. Pat. No. 5,754,381, which proposed a high-triggered current technology. On the right part of FIG. 5 is the modified NTLSCR (NMOS-trigger LSCR) structure and the left part of FIG. 5 is an NMOS. When an ESD zaps on the output pad, referring to the right portion of this figure, the N+ region of Dp2 could guide some current into VDD line and sink the current to raise the trigger current of the modified NTLSCR. This design could prevent the SCR from being triggered on by the system transient noise to avoid latch-up phenomenon when IC is in the normal operation condition.
In FIG. 6, the lateral SCR structure was disclosed in a US patent of U.S. Pat. No. 6,081,002. The structure of FIG. 6 is comprised of an NMOS and a PMOS, and the drain side 122 of the NMOS and the source side 134 of the PMOS are connected by silicide 136. The location of the drain of the NMOS is on the interface of the N well 104 and P substrate 102. The main highly doped regions of this lateral SCR structure are all defined by polysilicon gates.
The present invention proposes a lateral SCR device without shallow trench isolation on the conduction current flowing path, so that the drawback of the current flowing path is limited by the shallow trench isolation in prior lateral SCR device is overcome.
It is one object of the present invention to provide a method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process, in which one shallow trench isolation on the conduction current flowing path of the SCR device is removed and instead of a dummy gate, and thus a narrower anode-to-cathode spacing is obtained, so that the SCR device provides a quicker turn-on speed to discharge the ESD current.
It is another object of the present invention to provide a method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process, wherein there is no shallow trench isolation in the conduction current flowing path of the SCR device, so that the SCR device has a narrower anode-to-cathode spacing to save silicon area of the substrate occupied by the SCR device.
It is a further object of the present invention to provide a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process, which can be realized by only changing layout pattern in the mask layers, and fully process-compatible to general CMOS technologies.
In order to achieve the above objects, the present invention provides a method for forming a lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process. Firstly, providing a semiconductor substrate with a first conductive type and forming a plurality of shallow trench isolations in the substrate. Then, forming a first well with a second conductive type between one pair of the shallow trench isolations in the substrate. Afterward, forming a dummy gate above the first well on the substrate. Subsequently, forming a MOS-like gate with the second conductive type on the substrate beside the first well. Then, forming a first highly doped diffusion region with the second conductive type beside each side of the MOS-like gate in the substrate, one first diffusion region across one portion of the first well and one portion of the substrate and adjacent to one side of the dummy gate, while the other first diffusion region with opposite to the first diffusion region across the first well and the substrate and connected to a cathode terminal. Finally, forming a second highly doped diffusion region with the first conductive type beside the dummy gate with opposite to the first diffusion region adjacent to the dummy gate, the second diffusion region connected to an anode terminal.